JEE Main · 2023 · 13 Apr 2023 · Shift 1 · Semiconductors

The upper gate inverts $A$ to give $\overline{A}$ and the lower gate passes $B$; these feed a NAND gate, so

Reading the inputs interval by interval: before $t_1$ both $A=0$ and $B=0$, giving $Y=1$; between $t_1$ and $t_2$ the inputs are $A=0,B=1$, giving $Y=0$; from $t_2$ onward every interval has either $A=1$ or $B=0$, giving $Y=1$. The output therefore stays high except for a single low pulse between $t_1$ and $t_2$.