JEE Main · 2023 · 30 Jan 2023 · Shift 1 · Semiconductors

Each of the first two gates is a NAND with its two inputs tied together, so the upper gate delivers $\overline{A}$ and the lower gate delivers $\overline{B}$. These feed the third NAND, whose output is $Y=\overline{\overline{A}\cdot \overline{B}}=A+B$ by De Morgan's law, so the network behaves as a single OR gate. Following the two input trains through this rule, the output stands high in every interval where A or B (or both) is at logic $1$ and drops to zero only across the single stretch where A and B are simultaneously low. The output is thus the logical sum of the two inputs, high throughout except in that one common-low interval.