JEE Main · 2025 · 22 Jan 2025 · Shift 2 · Semiconductors

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To obtain the given truth table, following logic gate should be placed at G :
  1. (A)NOR Gate✓ Correct
  2. (B)AND Gate
  3. (C)NAND Gate
  4. (D)OR Gate

Answer: (A)

Solution

Inputs A and B first pass through a NOT-then-AND stage: the top AND gate takes A and , giving ; the bottom AND gate takes and B, giving . These two signals P and Q are the actual inputs to gate G, not A and B directly.

Evaluating P and Q for each row of the given table:

A=0, B=0: P = 0·1 = 0, Q = 1·0 = 0
A=0, B=1: P = 0·0 = 0, Q = 1·1 = 1
A=1, B=0: P = 1·1 = 1, Q = 0·0 = 0
A=1, B=1: P = 1·0 = 0, Q = 0·1 = 0

So (P,Q) takes the values (0,0), (0,1), (1,0), (0,0) across the four rows, and the required outputs are Y = 1, 0, 0, 1 respectively.

Testing a NOR gate at G, :
(0,0) → 1, (0,1) → 0, (1,0) → 0, (1,1) → 0

This reproduces Y = 1, 0, 0, 1 for every row of the table exactly, so gate G is a NOR gate.

JEE Main · 2025 · 22 Jan 2025 · Shift 2 · Single correct option

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