JEE Main · 2025 · 29 Jan 2025 · Shift 1 · Semiconductors

Label the two inputs A and B. From the circuit, the top gate is a NAND of A and B, giving $\overline{AB}$. A second branch passes A and B through an OR gate followed by a NOT gate, giving $\overline{A+B}$ (a NOR of A and B). These two signals, $\overline{AB}$ and $\overline{A+B}$, are fed into the final NAND gate, so


By De Morgan's theorem,


Since $AB$ is always contained in $A+B$, this simplifies to


Checking all four input combinations confirms $Y$ is 0 only when both A and B are 0, and 1 otherwise — the truth table of an OR gate.