JEE Main · 2025 · 02 Apr 2025 · Shift 2 · Semiconductors

Both inputs are $1$. The first gate is a NAND, and $\mathrm{NAND}(1,1)=0$; this $0$ is fed to the AND gate whose output is P, so $P=0$ regardless of its other input. Each input line is also inverted to $0$ and fed to the lower NOR gate, giving $\mathrm{NOR}(0,0)=1$; this $1$ reaches the final NOR gate that produces Q, and a NOR gate with any input equal to $1$ gives output $0$, so $Q=0$. The outputs are $P=0$ and $Q=0$.